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| PCA85232 LCD driver for low multiplex rates Rev. 1 -- 8 December 2010 Product data sheet 1. General description The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 160 segments. It can be easily cascaded for larger LCD applications. The PCA85232 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). AEC-Q100 compliant for automotive applications. 2. Features and benefits Single-chip LCD controller and driver for up to 640 elements Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing 160 segment drives: Up to eighty 7-segment numeric characters Up to forty 14-segment alphanumeric characters Any graphics of up to 640 elements May be cascaded for large LCD applications (up to 5120 elements possible) 160 x 4-bit RAM for display data storage Software programmable frame frequency in the range of 117 Hz to 176 Hz; factory calibrated Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs Internal LCD bias generation with voltage-follower buffers Selectable display bias configuration: static, 12, or 13 Wide power supply range: from 1.8 V to 5.5 V LCD and logic supplies may be separated Low power consumption, typical: IDD = 4 A, IDD(LCD) = 65 A 400 kHz I2C-bus interface Auto-incremental display data loading across device subaddress boundaries Versatile blinking modes Compatible with Chip-On-Glass (COG) technology No external components Two sets of backplane outputs for optimal COG configurations of the application 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15. NXP Semiconductors PCA85232 LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Package Name PCA85232U/2DA/Q1 bare die Description 197 bumps; 6.5 x 1.16 x 0.40 mm Delivery form Version chips with bumps in tray PCA85232U Type number 4. Marking Table 2. Marking codes Marking code PC85132/232-1 Type number PCA85232U/2DA/Q1 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 2 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 5. Block diagram BP0 BP1 BP2 BP3 S0 to S159 160 VLCD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL VSS LCD BIAS GENERATOR PCA85232 CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE DISPLAY RAM OSC OSCILLATOR POWER-ON RESET COMMAND DECODE WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT SCL SDA INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER SA0 SDAACK T1 T2 T3 VDD A0 A1 013aaa282 Fig 1. Block diagram of PCA85232 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 3 of 54 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 1 -- 8 December 2010 4 of 54 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. NXP Semiconductors 6. Pinning information 6.1 Pinning D4 S130 S80 BP3 BP1 BP2 BP0 S79 166 +y PCA85232 0 0 167 197 112 +x 30 D1 S131 S159 BP3 BP1 BP2 BP0 S0 CLK SYNC OSC T1 VDD A0 A1 SA0 SDAACK VLCD SCL T3 SDA VSS 013aaa283 S28 D2 T2 60 1 61 S29 D3 LCD driver for low multiplex rates PCA85232 Viewed from active side. For mechanical details, see Figure 32. Fig 2. Pinning diagram of PCA85232 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol SDAACK[1] SDA[1] SCL CLK VDD SYNC OSC T1, T2 and T3 A0 and A1 SA0 VSS[2] VLCD BP2 and BP0 S0 to S79 BP0, BP2, BP1, and BP3 S80 to S159 BP3 and BP1 [1] [2] Pin description Pin 1 to 3 4 to 6 7 to 9 10 11 to 13 14 15 16, 17 and 18 to 20 21, 22 23 24 to 26 27 to 29 30, 31 32 to 111 112 to 115 116 to 195 196, 197 Description I2C-bus acknowledge output I2C-bus serial data input I2C-bus serial clock input clock input and output supply voltage cascade synchronization input and output selection of internal or external clock dedicated testing pins; to be tied to VSS in application mode subaddress inputs I2C-bus slave address input ground supply voltage LCD supply voltage LCD backplane outputs LCD segment outputs LCD backplane outputs LCD segment outputs LCD backplane outputs For most applications SDA and SDAACK are shorted together (see Section 12.2). The substrate (rear side of the die) is connected to VSS and should be electrically isolated. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 5 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7. Functional description The PCA85232 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 160 segments. The display configurations possible with the PCA85232 depend on the required number of active backplane outputs. A selection of display configurations is given in Table 4. All of the display configurations given in Table 4 can be implemented in a typical system as shown in Figure 4. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 3. Table 4. Example of displays suitable for PCA85232 Selection of possible display configurations Icons 640 480 320 160 Digits/Characters 7-segment 14-segment 40 30 20 10 80 60 40 20 Dot matrix/ Elements 640 dots (4 x 160) 480 dots (3 x 160) 320 dots (2 x 160) 160 dots (1 x 160) Number of Backplanes 4 3 2 1 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 6 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates VDD R tr 2CB SDAACK VDD SDA SCL OSC VLCD 160 segment drives LCD PANEL HOST MICROPROCESSOR/ MICROCONTROLLER PCA85232 4 backplanes (up to 640 elements) A0 VSS A1 SA0 VSS 013aaa284 Fig 4. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCA85232. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application. 7.1 Power-On Reset (POR) At power-on the PCA85232 resets to the following starting conditions: * * * * * * * * All backplane and segment outputs are set to VLCD The selected drive mode is 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled If internal oscillator is selected (pin OSC connected to VSS), then there is no clock signal on pin CLK Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The center impedance is bypassed by switch if the 12 bias voltage level for the 1:2 multiplex drive mode configuration is selected. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 7 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Table 5. LCD drive mode static Biasing characteristics LCD bias Backplanes Levels configuration 1 2 3 4 4 4 static 1 1 1 1 2 3 3 3 Number of: V off ( RMS ) -----------------------V LCD 0 0.354 0.333 0.333 0.333 V on ( RMS -----------------------) V LCD 1 0.791 0.745 0.638 0.577 V on ( RMS ) D = -----------------------V off ( RMS ) 2.236 2.236 1.915 1.732 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = a 2 + 2a + n ----------------------------2 n x (1 + a) (1) V LCD where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2) V LCD Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ---------------------- = V off ( RMS ) PCA85232 (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1) Rev. 1 -- 8 December 2010 2 (3) (c) NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet 8 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1 1 2 2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with 21 bias is ---------- = 1.528 . 3 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: * 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS ) --------------------* 1:4 multiplex (12 bias): V LCD = ( 4 x 3 ) = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vlow) and the other at 90% relative transmission (at Vhigh), see Figure 5. For a good contrast performance, the following rules should be followed: V on ( RMS ) V high V off ( RMS ) V low (4) (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vlow and Vhigh are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 9 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 100 % 90 % Relative Transmission 10 % Vlow OFF SEGMENT Vhigh VRMS [V] ON SEGMENT 001aam358 GREY SEGMENT Fig 5. Electro-optical characteristic: relative transmission curve of the liquid PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 10 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 6. Tfr VLCD BP0 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD LCD segments state 1 (on) state 2 (off) state 1 0V -VLCD VLCD state 2 0V -VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn+1)(t) - VBP0(t). Voff(RMS) = 0 V. Fig 6. Static drive mode waveforms PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 11 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85232 allows the use of 12 bias or 13 bias in this mode as shown in Figure 7 and Figure 8. Tfr VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V -VLCD/2 -VLCD LCD segments state 2 VLCD VLCD/2 state 2 0V -VLCD/2 -VLCD (b) Resultant waveforms at LCD segment. 013aaa208 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD. Fig 7. Waveforms for the 1:2 multiplex drive mode with 12 bias PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 12 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Tfr BP0 VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 LCD segments state 1 state 2 BP1 Sn Sn+1 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:2 multiplex drive mode with 13 bias PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 13 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.4.3 1:3 multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure 9. Tfr VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD LCD segments BP0 state 1 state 2 BP1 BP2 Sn Sn+1 Sn+2 (b) Resultant waveforms at LCD segment. 013aaa210 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 9. Waveforms for the 1:3 multiplex drive mode with 13 bias PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 14 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 10. Tfr VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 (b) Resultant waveforms at LCD segment. 013aaa211 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 10. Waveforms for the 1:4 multiplex drive mode with 13 bias PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 15 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency fclk which either is derived from the built-in oscillator frequency fosc: f osc f clk = ------64 or equals an external clock frequency fclk(ext): f clk = f clk ( ext ) (7) (6) Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output from pin CLK provides the clock signal for cascaded PCA85232 in the system. However, the clock signal is only available at pin CLK, if the display is enabled. The display is enabled using the display enable bit (see Table 10). The output clock frequency is like specified in Table 19 with parameter fclk. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. 7.6 Timing and frame frequency The timing of the PCA85232 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCA85232 in the system. When the internal clock is used, the clock frequency can be programmed by software such that the frame frequency can be chosen in the range of 117 Hz to 176 Hz (see Table 16). The internal oscillator is calibrated within an accuracy of 5.1 % (at VDD = 5.0 V; Tamb = 30 C). The timing also generates the LCD frame frequency derived from an integer division of fclk (see Table 16). 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 16 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.8 Segment outputs The LCD drive section includes 160 segment outputs (S0 to S159) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display register. When less than 160 segment outputs are required the unused segment outputs must be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated in accordance with the selected LCD drive mode. * In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. * In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. * In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. * In static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In applications it is possible to use either the pins for the backplanes * on the top pin bar * on the bottom pin bar * or both of them to increase the driving strength of the device. When using all backplanes available they may be connected to the respective sibling (BP0 on the top pin bar with BP0 on the bottom pin bar and so on). 7.10 Display RAM The display RAM is a static 160 x 4 bit RAM which stores LCD data. There is a one-to-one correspondence between * the bits in the RAM bitmap and the LCD elements * the RAM columns and the segment outputs * the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. The display RAM bit map, Figure 11, shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the segment outputs S0 to S159. In multiplexed LCD applications the segment data of the first, second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 17 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates columns display RAM addresses/segment outputs (S) rows 0 display RAM rows/ backplane outputs 1 (BP) 2 3 013aaa220 0 1 2 3 4 155 156 157 158 159 The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs; and between the bits in a RAM word and the backplane outputs. Fig 11. Display RAM bitmap When display data is transmitted to the PCA85232 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 12: * In static drive mode the eight transmitted data bits are placed in row 0 as one byte. * In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit RAM words. * In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. * In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 18 of 54 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 1 -- 8 December 2010 19 of 54 PCA85232 NXP Semiconductors drive mode LCD segments LCD backplanes display RAM filling order columns display RAM address/segment outputs (s) byte1 transmitted display byte Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6 e d f a b g c Sn+1 Sn Sn+7 DP BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n c x x x n+1 b x x x n+2 a x x x n+3 f x x x n+4 g x x x n+5 e x x x n+6 d x x x n+7 DP x x x MSB cba f LSB g e d DP BP0 Sn 1:2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. a f g b columns display RAM address/segment outputs (s) byte1 byte2 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP Sn+1 multiplex Sn+2 Sn+3 e d c BP1 DP Sn+1 1:3 Sn+2 f a b g BP0 Sn n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2c 3x columns display RAM address/segment outputs (s) byte1 byte2 byte3 n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB e multiplex e d c BP1 DP BP2 LCD driver for low multiplex rates Sn 1:4 f a b g columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 BP0 BP2 n rows display RAM 0 a rows/backplane 1c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB egd multiplex e c d PCA85232 BP1 DP Sn+1 001aaj646 x = data bit unchanged Fig 12. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 8). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 12. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: * * * * In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses. 7.12 Subaddress counter The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to A0 and A1. The subaddress counter value is defined by the device-select command (see Table 13). If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85232 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. The hardware subaddress must not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector (see Table 14) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. * In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, row 2, and then row 3 * In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially * In 1:2 multiplex mode, rows 0 and 1 are selected * In static mode, row 0 is selected PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 20 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see Table 14). The input bank selector functions independently to the output bank selector. 7.15 Blinker The display blinking capabilities of the PCA85232 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 15). The blink frequencies are fractions of the clock frequency. The ratios between the clock and blink frequencies depend on the blink mode in which the device is operating (see Table 6). Table 6. Blink frequencies Assuming that fclk = 3.500 kHz. Blink mode off 1 Operating mode ratio f clk f blink = -------768 f clk f blink = ----------1536 f clk f blink = ----------3072 Blink frequency blinking off ~4.56 Hz 2 ~2.28 Hz 3 ~1.14 Hz An additional feature is for an arbitrary selection of LCD elements to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command (see Table 15). In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD elements can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blinking frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 10). 7.16 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 21 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully I2C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it may be possible that the acknowledge generated by the PCA85232 can't be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle is required, it is therefore necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level. By separating the acknowledge output from the serial data line (having the SDAACK open circuit) design efforts to generate a valid acknowledge level can be avoided. However, in that case the I2C-bus master has to be set up in such a way that it ignores the acknowledge cycle.2 The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13). SDA SCL data line stable; data valid change of data allowed mba607 Fig 13. Bit transfer 7.16.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 14. SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 14. Definition of START and STOP conditions 2. For further information, please consider the NXP application note: Ref. 1 "AN10170". All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. PCA85232 Product data sheet Rev. 1 -- 8 December 2010 22 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.16.2 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 15. MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 15. System configuration 7.16.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. * A slave receiver which is addressed must generate an acknowledge after the reception of each byte. * Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). * A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 16. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 16. Acknowledgement on the I2C-bus PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 23 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 7.16.4 I2C-bus controller The PCA85232 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA85232 are the acknowledge signals from the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data, and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0 and A1 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0 and A1 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. 7.16.5 Input filters To enhance noise immunity in electrical adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.16.6 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85232.The entire I2C-bus slave address byte is shown in Table 7. Table 7. Bit I2C slave address byte Slave address 7 MSB 0 1 1 1 0 0 SA0 6 5 4 3 2 1 0 LSB R/W The PCA85232 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 will respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1). Having two reserved slave addresses allows the following on the same I2C-bus: * Up to 8 PCA85232 on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex on the same I2C-bus The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCA85232 slave addresses available. All PCA85232 with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCA85232 with the alternative SA0 level ignore the whole I2C-bus transfer. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 24 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates R/W = 0 slave address S CR S011100A0A OS 0 control byte RAM/command byte M AS B L SP B EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP c) transmit one command byte and two RAM date bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP mgl752 Fig 17. I2C-bus protocol After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data. Table 8. Bit 7 Control byte description Symbol CO 0 1 6 RS 0 1 5 to 0 Value Description continue bit last control byte control bytes continue register selection command register data register not relevant MSB 7 6 5 4 3 2 1 LSB 0 CO RS not relevant mgl753 Fig 18. Control byte format In this way it is possible to configure the device and then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCA85232 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter; see Section 7.11 and Section 7.12. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 25 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates The acknowledgement after each byte is made only by the (A0 and A1) addressed PCA85232. After the last (display) byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access. 7.17 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCA85232 are defined in Table 9. Table 9. Command Bit mode-set load-data-pointer-MSB load-data-pointer-LSB device-select bank-select blink-select frequency-prescaler Table 10. Bit 7 to 4 3 Definition of PCA85232 commands Operation code 7 1 0 0 1 1 1 1 6 1 0 1 1 1 1 1 5 0 0 0 1 1 1 1 4 0 0 0 0 1 1 0 3 E P[7:4] P[3:0] 0 1 0 1 0 0 AB F[2:0] A[1:0] I O BF[1:0] 2 B 1 M[1:0] 0 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Reference Mode-set command bit description Symbol E 0[1] 1 Value 1100 Description fixed value display status disabled (blank)[2] enabled LCD bias configuration[3] 0[1] 1 1 1 3 bias 2 2 B bias 1 to 0 M[1:0] 01 10 11 00[1] LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2 1:4 multiplex; BP0, BP1, BP2, BP3 [1] [2] [3] Power-on and reset value. The possibility to disable the display allows implementation of blinking under external control; the enable bit determines also whether the internal clock signal is available at the CLK pin (see Section 7.5.1). Not applicable for static drive mode. Table 11. Bit 7 to 4 3 to 0 Load-data-pointer-MSB command bit description Symbol P[7:4] Value 0000 0000[1] 1001 to Description fixed value P7 to P4 defines the first 4 (most significant) bits of the data pointer that indicates one of the 160 display RAM addresses [1] PCA85232 Power-on and reset value. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 26 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Load-data-pointer-LSB command bit description Symbol P[3:0] Value 0100 0000[1] 1111 to Description fixed value P3 to P0 defines the last 4 (least significant) bits of the data pointer that indicates one of the 160 display RAM addresses Table 12. Bit 7 to 4 3 to 0 [1] Power-on and reset value. Table 13. Bit 7 to 2 1 to 0 Device-select command bit description Symbol A[1:0] Value 111000 00[1] to 11 Description fixed value two bits of immediate data, bits A0 to A1, are transferred to the subaddress counter to define one of four hardware subaddresses (see Table 20) [1] Power-on and reset value. Table 14. Bit 7 to 2 1 Bank-select command bit description Symbol I 0[2] 1 Value 111110 Description Static fixed value input bank selection; storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex[1] 0 O 0[2] 1 output bank selection; retrieval of LCD display data [1] [2] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Power-on and reset value. Table 15. Bit 7 to 3 2 Blink-select command bit description Symbol AB 0[1] 1 Value 11110 Description fixed value blink mode selection normal blinking[2] alternate RAM bank blinking[3] blink frequency selection 00[1] 01 10 11 off 1 2 3 1 to 0 BF[1:0] [1] [2] [3] Power-on and reset value. Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 27 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Frame-frequency prescaler Symbol F[2:0] 000 Value 11101 Description Nominal frame frequency[1] Equation fixed value defines the division factor for the frame frequency (ffr) 117 Hz 64 f clk f fr = ----- x ------80 24 64 f clk f fr = ----- x ------74 24 64 f clk f fr = ----- x ------68 24 f clk f fr = ------24 64 f clk f fr = ----- x ------60 24 64 f clk f fr = ----- x ------56 24 64 f clk f fr = ----- x ------53 24 f clk f fr = ------24 Table 16. Bit 7 to 4 3 to 0 001 126 Hz 010 011[2] 137 Hz 146 Hz 100 156 Hz 101 167 Hz 110 176 Hz 111 146 Hz [1] [2] Nominal frame frequency calculated for an internal operating frequency of 3.5 kHz. Power-on and reset value. 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA85232 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 28 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 8. Internal circuitry VLCD S0 to S159, BP0 to BP3 VSS VSS VDD VDD SYNC, T1, T2, A0, A1, OSC, CLK, SA0 VSS SDAACK, SCL, SDA, T3, VLCD VSS 013aaa221 Fig 19. Device protection diagram PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 29 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 17. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD IDD VLCD Vi supply voltage supply current LCD supply voltage input voltage on pins CLK, SYNC, SA0, OSC, SDA, SCL, A0, A1, T1, T2, and T3 on pins S0 to S159 and BP0 to BP3 on pins SDAACK, CLK, SYNC IO ISS Ptot P/out VESD output current ground supply current total power dissipation power dissipation per output electrostatic discharge voltage latch-up current storage temperature operating temperature HBM MM Ilu Tstg Toper [1] [2] [3] [4] [5] [2] Conditions Min -0.5 -50 -0.5 -50 -0.5 Max +6.5 +50 +9.0 +50 +6.5 Unit V mA V mA V IDD(LCD) LCD supply current II VO input current output voltage -10 -0.5 -0.5 -10 -50 -65 -40 +10 +9.0 +6.5 +10 +50 400 100 4500 250 200 +150 +95 mA V V mA mA mW mW V V mA C C [3] [4] [5] Stresses above these values listed may cause permanent damage to the device. Pass level; Human Body Model (HBM) according to Ref. 6 "JESD22-A114". Pass level; Machine Model (MM), according to Ref. 7 "JESD22-A115". Pass level; latch-up testing, according to Ref. 8 "JESD78" at maximum ambient temperature (Tamb(max) = 95 C). According to the NXP store and transport requirements (see Ref. 10 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 30 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 10. Static characteristics Table 18. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = -40 C to +95 C; unless otherwise specified. Symbol Parameter Supplies VDD VLCD IDD IDD(LCD) Logic VI VIH VIL VO VOH VOL IOH IOL input voltage HIGH-level input voltage LOW-level input voltage output voltage on pins SDA and SCL all other input pins on pins CLK, SYNC, OSC, A0, A1, SA0, SCL, and SDA on pins CLK, SYNC, OSC, A0, A1, SA0, SCL, and SDA on pins CLK and SYNC on pin SDAACK HIGH-level output voltage on pin SYNC, CLK LOW-level output voltage on pin SYNC, CLK, SDAACK HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK LOW-level output current output sink current; on pins CLK and SYNC VOL = 0.4 V; VDD = 5 V on pin SDAACK VDD 2 V; VOL = 0.2VDD 2 V < VDD < 3 V; VOL = 0.4 V VDD 3 V; VOL = 0.4 V VPOR IL power-on reset voltage leakage current VI = VDD or VSS; on pin OSC, CLK, A0, A1, SA0, SDA, and SCL 3 3 6 1.0 -1 1.3 1.6 +1 mA mA mA V A 1.5 mA -0.5 -0.5 0.7VDD -0.5 -0.5 0.8VDD VSS 1.5 +5.5 0.3VDD V V V VDD + 0.5 V supply voltage LCD supply voltage supply current LCD supply current fclk(ext) = 3.500 kHz with internal oscillator running fclk(ext) = 3.500 kHz with internal oscillator running [1][2][3] [1][3] [1][2][4] [1][4] Conditions Min 1.8 1.8 - Typ - Max 5.5 8.0 30 80 60 80 Unit V V A A A A VDD + 0.5 V +5.5 VDD 0.2VDD V V V mA PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 31 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Table 18. Static characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = -40 C to +95 C; unless otherwise specified. Symbol Parameter LCD outputs VO RO output voltage variation output resistance on pins BP0 to BP3 and S0 to S159 VLCD = 5 V on pins BP0 to BP3 on pins S0 to S159 [1] [2] [3] [4] [5] [6] [5][6] Conditions Min -30 - Typ 1.5 2.0 Max +30 5 5 Unit mV k k LCD outputs are open-circuit; inputs at VSS or VDD; I2C-bus inactive; VLCD = 8.0 V, VDD = 5.0 V and RAM written with all logic 1. External clock with 50 % duty factor. For typical values, see Figure 20 For typical values, see Figure 21 Variation between any 2 backplanes on a given voltage level; static measured. Variation between any 2 segments on a given voltage level; static measured. 25 IDD (A) 20 (1) 001aal525 15 10 5 (2) 0 1 2 3 4 5 VDD (V) 6 (1) IDD internal is measured with the internal oscillator. (2) IDD external is measured with an external clock. Tamb = 30 C; 1:4 multiplex; VLCD = 8 V; all RAM written with logic 1; no display connected. Fig 20. IDD with respect to VDD PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 32 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 70 IDD(LCD) (A) 50 001aal526 30 10 1 3 5 7 VLCD (V) 9 Tamb = 30 C; 1:4 multiplex; all RAM written with logic 1; no display connected; fclk = 3.5 kHz.or fclk(ext) = 3.500 kHz. Fig 21. IDD(LCD) with respect to VLCD PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 33 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 11. Dynamic characteristics Table 19. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = -40 C to +95 C; unless otherwise specified. Symbol fclk fclk(ext) tclk(H) tclk(L) ffr Parameter clock frequency external clock frequency HIGH-level clock time LOW-level clock time frame frequency variation external clock source used external clock source used VDD = 5 V 0.5 V ffr = 146 Hz; Tamb = 30 C ffr = 135 Hz; Tamb = 95 C ffr = 157 Hz; Tamb = -40 C tPD(SYNC_N) SYNC propagation delay tSYNC_NL tPD(drv) fSCL tBUF tHD;STA tSU;STA tVD;ACK tLOW tHIGH tf tr Cb tSU;DAT tHD;DAT tSU;STO tSP SYNC LOW time driver propagation delay I2C-bus[5] 1.3 0.6 0.6 1.3 0.6 of both SDA and SCL signals of both SDA and SCL signals 200 0 0.6 400 0.9 0.3 0.3 400 50 kHz s s s s s s s s pF ns ns s ns SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition data valid acknowledge time LOW period of the SCL clock HIGH period of the SCL clock fall time rise time capacitive load for each bus line data set-up time data hold time set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter Typical output duty factor: 50 % measured at the CLK output pin. For the respective frame frequency ffr see Table 16. For the characteristics of VDD at a fixed temperature or of the temperature at a fixed VDD, see Figure 22 and Figure 23. For fCLK(ext) > 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor should be between 100 k and 1 M. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Conditions on pin CLK; VDD = 5 V 0.5 V [1][2][3] Min Typ Max Unit 3050 3500 4052 Hz 700 100 100 -5.1 -6.2 -7.8 100 30 10 5000 Hz +5.1 +6.9 +7.6 s s % % % ns s s [4] VLCD = 5 V - Timing characteristics: [1] [2] [3] [4] [5] PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 34 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 3540 fclk (Hz) 3500 001aal527 3460 3420 3380 3340 1 2 3 4 5 VDD (V) 6 Tamb = 30 C. Fig 22. Typical clock frequency (fclk) with respect to VDD 170 ffr (Hz) 160 001aal481 7.6 % 150 7.8 % 5.1 % 5.1 % max typ 140 6.9 % min 130 6.2 % 120 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Condition: VDD = 5 V 0.5 V; frame frequency prescaler = 011; 146 Hz typical. The frame frequency (ffr) is calculated from the clock frequency (fclk) according to the equations described in Table 16. Fig 23. Frame frequency variation PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 35 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 1 / fCLK tclk(H) CLK tclk(L) 0.7 VDD 0.3 VDD SYNC tPD(SYNC_N) tSYNC_NL 0.7 VDD 0.3 VDD 0.5 V BP0 to BP3, and S0 to S159 tPD(drv) (VDD = 5 V) 0.5 V 001aah848 Fig 24. Driver timing waveforms tf SDA 70 % 30 % tf 70 % 30 % tHD;STA S tr 70 % 30 % tHD;DAT tSU;DAT cont. tVD;ACK tr tHIGH 70 % 30 % tLOW 70 % 30 % 9th clock SCL 70 % 30 % cont. 1 / fSCL 1st clock cycle tBUF SDA tVD;ACK tSU;STA tHD;STA tSP 70 % 30 % tSU;STO SCL Sr P 9th clock S 013aaa110 Fig 25. I2C-bus timing waveforms when SDA and SDAACK are connected PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 36 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 12. Application information 12.1 Pull-up resistor sizing on I2C-bus 12.1.1 Max value of pull-up resistor The bus capacitance (Cb) is the total capacitance of wire, connections, and pins. This capacitance on pin SDA limits the maximum value of the pull-up resistor (RPU) due to the specified rise time. According to the I2C-bus specification the rise time (tr) is defined between the VDD related input threshold of VIL = 0.3VDD and VIH = 0.7VDD. The value for tr(max) is 300 ns. tr will be calculated with Equation 8: t r = t2 - t1 whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are derivatives of the functions V(t1) and V(t2): V ( t1 ) = 0.3V DD = V DD ( 1 - e V ( t2 ) = 0.7V DD = V DD ( 1 - e with the results of t1 = - R PU C b x ln(0.7) t2 = - R PU C b x ln(0.3) t r = - R PU C b x ln(0.3) + R PU C b x ln(0.7) RPU(max) is a function of the rise time (tr) and the bus capacitance (Cb) and will be calculated with Equation 14: tr -9 - 300 x 10 R PU ( max ) = ---------------------- = ------------------------0.8473C b 0.8473C b (14) (11) (12) (13) -t1 R PU C b -t2 R PU C b (8) ) ) (9) (10) 12.1.2 Min value of pull-up resistor The supply voltage limits the minimum value of resistor RPU due to the specified minimum sink current (see value of IOL on pin SDAACK in Table 18). RPU(min) as a function of VDD is calculated with Equation 15: V DD - V OL R PU ( min ) = ------------------------I OL (15) The designer now has the minimum and maximum value of RPU. The values for RPU(max) and RPU(min) are shown in Figure 26 and Figure 27. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 37 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 6 RPU(max) (k) 5 001aak441 4 3 2 1 0 20 60 100 140 180 220 260 300 340 380 420 460 500 Cb (pF) Fig 26. Values for RPU(max) 6 RPU(min) (k) 5 001aak440 4 3 2 1 0 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) Fig 27. Values for RPU(min) 12.2 SDA and SDAACK configuration The Serial DAta line (SDA) and the I2C-bus acknowledge line (SDAACK) are split. Both lines can be connected together to facilitate a single line SDA. SDA SDAACK two wire mode SDA SDAACK single wire mode 013aaa111 Fig 28. SDA, SDAACK configurations PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 38 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 12.3 Cascaded operation In large display configurations, up to 8 PCA85232 can be distinguished on the same I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable I2C-bus slave address (SA0). Table 20. Cluster 1 Addressing cascaded PCA85232 Bit SA0 0 Pin A1 0 0 1 1 2 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 When cascaded PCA85232 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA85232 of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 29). For display sizes that are not multiple of 640 elements, a mixed cascaded system can be considered containing only devices like PCA85232 and PCA85133. Depending on the application, one must take care of the software commands compatibility and pin connection compatibility. The SYNC line is provided to maintain the correct synchronization between all cascaded PCA85232. This synchronization is guaranteed after the Power-On Reset (POR). The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCA85232 with different SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCA85232 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCA85232 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCA85232 are shown in Figure 31. When using an external clock signal with high frequencies (fclk(ext) > 4 kHz) it is recommended to have an external pull-up resistor between pin SYNC and pin VDD (see Table 19). This resistor should be present even when no cascading configuration is used! When using it in a cascaded configuration, care must be taken not to route the SYNC signal to close to noisy signals. The contact resistance between the SYNC pads of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 21 shows the limiting values for contact resistance. PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 39 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates SYNC contact resistance Maximum contact resistance 6000 2200 1200 Table 21. 2 3 to 5 6 to 8 Number of devices In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is connected to VSS so that this device uses its internal clock to generate a clock signal at the CLK pin. The other PCA85232 devices are having the OSC pin connected to VDD, meaning that these devices are ready to receive external clock, the signal being provided by the device with subaddress 0. In the case that the master is providing the clock signal to the slave devices, care must be taken that the sending of display enable or disable will be received by both, the master and the slaves at the same time. When the display is disabled the output from pin CLK is disabled too. The disconnection of the clock may result in a DC component for the display. Alternatively, the schematic can be also constructed such that all the devices have OSC pin connected to VDD and thus an external CLK being provided for the system (all devices connected to the same external CLK). A configuration where SYNC is connected but all PCA85232 are using the internal clock (OSC pin tied to VSS) is not recommended and may lead to display artifacts! PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 40 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2Cb SDA SCL SYNC CLK OSC A1 VLCD segment drivers PCA85232 (2) backplanes (open-circuit) SA0 VSS LCD PANEL R VDD VLCD HOST MICROPROCESSOR/ MICROCONTROLLER segment drivers PCA85232 (1) backplanes 013aaa285 A0 VSS A1 SA0 VSS (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 29. Cascaded configuration with two PCA85232 using the internal clock of the master PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 41 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2Cb SDA SCL SYNC CLK OSC A1 VLCD segment drives PCA85133 (2) backplanes (open-circuit) A2 SA0 VSS LCD PANEL R VDD VLCD HOST MICROPROCESSOR/ MICROCONTROLLER segment drives PCA85232 (1) backplanes 013aaa286 A0 VSS A1 SA0 VSS (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 30. Cascaded configuration with one PCA85232 and one PCA85133 using the internal clock of the master PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 42 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1:2 multiplex drive mode BP2 (1/3 bias) SYNC (c) 1:3 multiplex drive mode BP3 (1/3 bias) SYNC (d) 1:4 multiplex drive mode 001aaj498 Fig 31. Synchronization of the cascade for the various PCA85232 drive modes PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 43 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 13. Bare die outline Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm PCA85232U D 166 +y +x 0 S1 E 61 X C1 0 Marking code: PC85132/232-1 167 197 1 Y 60 A b e e1 A2 A1 L detail Y detail X 0 Dimensions Unit mm A(1) A1(1) A2(1) b(1) D 6.5 E e(1) e1(1) 1 scale L(1) 2 mm max 0.018 nom 0.40 0.015 0.380 0.0338 min 0.012 1.16 0.054 0.2025 0.090 Note 1. Dimension not drawn to scale. Outline version PCA85232U References IEC JEDEC JEITA European projection PCA85232_do Issue date 10-02-03 Fig 32. Bare die outline of PCA85232 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 44 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol SDAACK SDAACK SDAACK SDA SDA SDA SCL SCL SCL CLK VDD VDD VDD SYNC OSC T1 T2 T3 T3 T3 A0 A1 SA0 VSS VSS VSS VLCD VLCD VLCD BP2 BP0 S0 S1 S2 S3 S4 S5 S6 S7 PCA85232 Bump 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 X (m) -1165.3 -1111.3 -1057.3 -854.8 -800.8 -746.8 -575.8 -521.8 -467.8 -316.2 -204.1 -150.1 -96.1 6.9 119.4 203.1 286.8 389.9 443.9 497.9 640.5 724.2 807.9 893.0 947.0 1001.0 1107.2 1161.2 1215.2 1303.4 1357.4 1411.4 1465.4 1519.4 1573.4 1627.4 1681.4 1735.4 1789.4 Y (m) -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 Symbol S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 BP0 BP2 BP1 BP3 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 Bump 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 X (m) 750.2 696.2 642.2 588.2 534.2 480.2 426.2 372.2 318.2 264.2 210.2 156.2 86.8 32.8 -21.2 -75.2 -190.7 -244.7 -298.7 -352.7 -406.7 -460.7 -514.7 -568.7 -622.7 -676.7 -730.7 -784.7 -838.7 -892.7 -946.7 -1000.7 -1054.7 -1108.7 -1224.2 -1278.2 -1332.2 -1386.2 -1440.2 Y (m) 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 45 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Table 22. Bump locations ...continued All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 PCA85232 Bump 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 X (m) 1843.4 1897.4 1951.4 2005.4 2059.4 2113.4 2167.4 2221.4 2363.9 2417.9 2471.9 2525.9 2579.9 2633.9 2687.9 2741.9 2795.9 2849.9 2903.9 2957.9 3011.9 3067.7 3013.7 2959.7 2905.7 2851.7 2797.7 2743.7 2689.7 2635.7 2520.2 2466.2 2412.2 2358.2 2304.2 2250.2 2196.2 2142.2 2088.2 Y (m) -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 Symbol S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 Bump 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 X (m) -1494.2 -1548.2 -1602.2 -1656.2 -1710.2 -1764.2 -1818.2 -1872.2 -1926.2 -1980.2 -2034.2 -2088.2 -2142.2 -2284.7 -2338.7 -2392.7 -2446.7 -2500.7 -2554.7 -2608.7 -2662.7 -2716.7 -2770.7 -2824.7 -2878.7 -2932.7 -2986.7 -3040.7 -3025.2 -2971.2 -2917.2 -2863.2 -2809.2 -2755.2 -2701.2 -2647.2 -2593.2 -2539.2 -2485.2 Y (m) 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 46 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Table 22. Bump locations ...continued All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 Bump 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 X (m) 2034.2 1891.7 1837.7 1783.7 1729.7 1675.7 1621.7 1567.7 1513.7 1459.7 1405.7 1351.7 1297.7 1243.7 1189.7 1135.7 1081.7 1027.7 973.7 858.2 804.2 Y (m) 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 481.5 Symbol S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 BP3 BP1 Bump 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 X (m) -2431.2 -2377.2 -2234.7 -2180.7 -2126.7 -2072.7 -2018.7 -1964.7 -1910.7 -1856.7 -1802.7 -1748.7 -1694.7 -1640.7 -1586.7 -1532.7 -1478.7 -1424.7 -1370.7 -1316.7 Y (m) -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 -481.5 The dummy pins are connected to the segments shown (see Table 23) but are not tested. Table 23. Dummy bumps All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol D1 D2 D3 D4 Connected to pin S131 S28 S29 S130 X (m) -3079.2 3065.9 3121.7 -3094.7 Y (m) -481.5 -481.5 481.5 481.5 The alignment marks are shown in Table 24. Table 24. Alignment marking All x/y coordinates represent the position of the REF point (see Figure 33) with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol S1 C1 Size (m) 121.5 x 121.5 121.5 x 121.5 X (m) -2733.75 2603.7 Y (m) -47.25 -47.25 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 47 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates REF S1 REF C1 001aah849 Fig 33. Alignment marks PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 48 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 14. Packing information Table 25. Symbol A B C D E F x y Tray dimensions (see Figure 34) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 8.8 mm 3.6 mm 6.65 mm 1.31 mm 50.8 mm 50.8 mm 5 12 A C D B F y E x 001aah890 Fig 34. Tray details PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 49 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates marking code 001aaj643 Fig 35. Tray alignment 15. Abbreviations Table 26. Acronym AEC COG DC HBM I2C IC ITO LCD LSB MM MSB POR RC RAM RMS SCL SDA Abbreviations Description Automotive Electronics Council Chip-On-Glass Direct Current Human Body Model Inter-Integrated Circuit Integrated Circuit Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Power-On Reset Resistance and Capacitance Random Access Memory Root Mean Square Serial CLock line Serial DAta line PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 50 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 16. References [1] [2] [3] [4] [5] [6] [7] [8] [9] AN10170 -- Design guidelines for COG modules with NXP monochrome LCD drivers AN10706 -- Handling bare die AN10853 -- ESD and EMC sensitivity of IC IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 -- NXP store and transport requirements [11] UM10204 -- I2C-bus specification and user manual 17. Revision history Table 27. Revision history Release date 20101208 Data sheet status Product data sheet Change notice Supersedes Document ID PCA85232 v.1 PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 51 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 52 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA85232 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 8 December 2010 53 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 7 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.3.1 Electro-optical performance . . . . . . . . . . . . . . . 9 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 11 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 15 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 Timing and frame frequency . . . . . . . . . . . . . . 16 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 17 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 20 7.13 Output bank selector . . . . . . . . . . . . . . . . . . . 20 7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 21 7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 21 7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.1.1 START and STOP conditions . . . . . . . . . . . . . 22 7.16.2 System configuration . . . . . . . . . . . . . . . . . . . 23 7.16.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16.4 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 24 7.16.5 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.16.6 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24 7.17 Command decoder . . . . . . . . . . . . . . . . . . . . . 26 7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 28 8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 31 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 34 12 Application information. . . . . . . . . . . . . . . . . . 37 12.1 12.1.1 12.1.2 12.2 12.3 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Pull-up resistor sizing on I2C-bus. . . . . . . . . . Max value of pull-up resistor . . . . . . . . . . . . . Min value of pull-up resistor . . . . . . . . . . . . . . SDA and SDAACK configuration . . . . . . . . . . Cascaded operation. . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38 39 44 49 50 51 51 52 52 52 52 53 53 54 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 December 2010 Document identifier: PCA85232 |
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